High-level hot carrier reliability-driven synthesis using macro-models

Author

Karnik, Tanay ; Teng, Chin-Chi ; Kang, Sung-Mo

Author_Institution

Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

65

Lastpage

68

Abstract

We present a systematic method to incorporate hot carrier reliability issues in high-level design automation. This method attempts to iteratively redesign the given high-level circuit to achieve better long-term reliability using macro-models of standard circuit elements. A reliability simulation tool, ILLIADS-R, is used to develop those macro-models. The method has been applied to various high-level sequential circuits. The results show the iterative reliability improvement using our capacitance reduction method

Keywords

VLSI; circuit CAD; circuit analysis computing; digital simulation; high level synthesis; hot carriers; integrated circuit design; integrated circuit reliability; logic CAD; sequential circuits; IC design; ILLIADS-R; VLSI; capacitance reduction method; high-level design automation; hot carrier reliability; iterative reliability improvement; long-term reliability; macro-models; reliability simulation tool; sequential circuits; standard circuit elements; CMOS digital integrated circuits; CMOS logic circuits; Circuit synthesis; Degradation; Design automation; Digital circuits; Hot carrier effects; Hot carriers; Propagation delay; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518138

Filename

518138