Title :
Hot-carrier induced degradation of critical paths modeled by rule-based analysis
Author :
Kuusinen, Scott B. ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
An implementation of simple hot carrier rules is presented with the intent of providing insight into reliability problems as early in the design process as possible. To that end, these rules have been incorporated into BERT, a circuit reliability simulator, using a timing simulator as the simulation engine. This allows for quick estimation of problem points in the critical path of large circuits. Furthermore, by exploiting the inverting property of CMOS circuitry, it is possible to remove some of the estimation problems that can arise from false paths. By separating analysis into rising and falling waveforms, and partitioning the circuit into channel connected components, it is possible to prevent analysis of clearly impossible paths
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; hot carriers; integrated circuit design; integrated circuit reliability; knowledge based systems; timing; BERT; CMOS circuitry; VLSI; channel connected components; circuit reliability simulator; critical paths; false paths; hot-carrier induced degradation; reliability problems; rule-based analysis; simulation engine; timing simulator; Circuit simulation; Degradation; Hot carriers; Integrated circuit reliability; MOS devices; Predictive models; Propagation delay; Time factors; Timing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518139
