New approaches for on-chip power switching noise reduction

The effect of power supply switching noise is gaining importance with increasing switching speeds and density of VLSI chips. Yet, today´s design methodology does not adequately address this problem at chip level. This paper proposes two approaches for on-chip power switching noise reduction. The first approach aims at reducing Delta-I noise by inserting decoupling capacitors in an optimized manner. The second approach reduces the switching noise by wire-sizing power bus segments near each power pin. Both approaches are assessed by simulation of a circuit, in which power supply rails are modeled as lossy transmission lines. The results of the simulated example demonstrate the effectiveness of our approaches