DocumentCode
2719707
Title
A power optimized 13-bit 5M samples/s pipelined analog to digital converter in 1.2 μm CMOS
Author
Cline, David W. ; Gray, Paul R.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1995
fDate
1-4 May 1995
Firstpage
219
Lastpage
222
Abstract
A 13-bit 5-MHz pipelined analog to digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier architecture and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak SNDR and 82.9 dB dynamic range. INL is 0.8 LSB and DNL is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply
Keywords
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 1.2 micron; 13 bit; 166 mW; 5 MHz; 5 V; CMOS process; analog/digital converter; pipelined ADC; power optimized 13-bit 5M samples/s; residue amplifier architecture; Analog-digital conversion; Calibration; Capacitors; Dynamic range; Linearity; Pipelines; Power dissipation; Sampling methods; Signal processing; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518172
Filename
518172
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