• DocumentCode
    2719910
  • Title

    Timing verification of dynamic circuits

  • Author

    Venkat, Kumar ; Chen, Liang ; Lin, Ichiang ; Mistry, Piyush ; Madhani, Pravin ; Sato, Katsuya

  • Author_Institution
    Silicon Graphics Inc., Mountain View, CA, USA
  • fYear
    1995
  • fDate
    1-4 May 1995
  • Firstpage
    271
  • Lastpage
    274
  • Abstract
    A complete set of algorithmic rules is presented for timing verification of domino-style precharge logic circuits. These rules include identification of dynamic nodes in a circuit, generation of timing constraints based on the operating environment of a dynamic gate, and verification of the timing constraints as part of a complete timing verification process. An important part of this approach is propagation of gated-clock pulses which are used extensively in dynamic circuits. The algorithms have been implemented in a new static timing verifier called MTV (Mips Timing Verifier) which is targeted towards verification of custom microprocessor circuits. MTV has been demonstrated to be useful on a number of real-world custom circuits
  • Keywords
    application specific integrated circuits; logic circuits; timing; MTV; Mips Timing Verifier; algorithmic rules; custom microprocessor circuits; domino-style precharge logic circuits; dynamic circuits; dynamic gate; dynamic nodes; gated-clock pulses; static timing verifier; timing constraints; timing verification; Clocks; Coupling circuits; Logic; Microprocessors; Pulse circuits; Pulse generation; Silicon; Space vector pulse width modulation; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-7803-2584-2
  • Type

    conf

  • DOI
    10.1109/CICC.1995.518184
  • Filename
    518184