Title :
A single-chip concatenated FEC decoder
Author :
Luthi, Daniel A. ; Mogre, Advait ; Ben-Efraim, Nadav ; Gupta, Alok
Author_Institution :
LSI Logic Corp., Milpitas, CA, USA
Abstract :
A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The device has been fabricated in a 0.6 μm CMOS cell-based technology and is fully functional at data rates of 73 Mbits/sec at 70°C and 4.75 V
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; Viterbi decoding; application specific integrated circuits; concatenated codes; convolutional codes; direct broadcasting by satellite; forward error correction; synchronisation; television receivers; 0.6 micron; 4.75 V; 70 degC; 73 Mbit/s; CMOS cell-based technology; Reed-Solomon decoding; Viterbi decoding; concatenated FEC decoder; convolutional deinterleaving; data rates; data stream synchronization; descrambling; digital satellite receiver system; forward error correction functions; CMOS technology; Concatenated codes; Convolutional codes; Decoding; Digital video broadcasting; Forward error correction; Quadrature phase shift keying; Reed-Solomon codes; Satellites; Viterbi algorithm;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518187
