CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

Author

Thamsirianunt, Manop ; Kwasniewski, Tadeusz A.

Author_Institution

PMC-Sierra Inc., Burnaby, BC, Canada

fYear

1995

fDate

1-4 May 1995

Firstpage

331

Lastpage

334

Abstract

We report on a CMOS inductorless VCO design with an emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The measurement results of three VCOs implemented in 1.2 μm CMOS technology verify the simulation predictions. The simplest VCO architecture exhibits 926 MHz operation with -83 dBc/Hz phase noise (100 kHz carrier offset) and 5 mW (5 volts) power consumption

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; digital radio; frequency synthesizers; integrated circuit noise; land mobile radio; mobile radio; phase locked loops; phase noise; voltage-controlled oscillators; 1.2 micron; 5 V; 5 mW; 926 GHz; CMOS VCOs; PLL frequency synthesis; VCO architecture; design methodology; differential circuits; digital mobile radio communications; gigahertz-range circuits; high-speed operation; inductorless VCO design; low-noise operation; low-power consumption; optimization; phase noise; portable wireless equipment; ring oscillator; CMOS technology; Circuit synthesis; Design methodology; Design optimization; Frequency synthesizers; Land mobile radio; Phase locked loops; Predictive models; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518197

Filename

518197