Title :
Application of temporal logic to the assistance of hardware logic design
Author :
Fujita, Masahiro
Author_Institution :
Fujitsu Lab. Ltd., Kawasaki, Japan
Abstract :
The specification of digital systems in temporal logic, a verification method between specification and gate-level designs, and a method for synthesizing state diagrams from specification are presented. Timing relations shown usually be timing diagrams can be described, and verification and synthesis can be done automatically. A hardware description language called Tokio, which is based on temporal logic and is an extension of Prolog, is also presented. The above techniques can be applied to Tokio.<>
Keywords :
formal logic; logic design; Prolog; Tokio; digital systems; gate-level designs; hardware description language; hardware logic design; specification; state diagrams synthesis; temporal logic; timing diagrams; verification method; Computational modeling; Delay; Digital systems; Hardware design languages; Laboratories; Logic design; Production; Sequential circuits; Timing; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on
Conference_Location :
Palma de Mallorca, Spain
Print_ISBN :
0-8186-0859-5
DOI :
10.1109/ISMVL.1988.5182
