Dual threshold delay model for nonlinear device characterization

Author

Tomita, Yasuhiro ; Iwanishi, Nobufusa ; Yamaguchi, Ryuichi ; Edamatsu, Hisakazu

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1995

fDate

1-4 May 1995

Firstpage

371

Lastpage

374

Abstract

We propose a dual threshold delay model for accurate timing definition for cell-based LSI designs by introducing dual threshold voltage definitions for each cell and by making cell delay and wire delay positive. Our model aims at high density and low power design of sub-half micron CMOS devices. Further more, this model solves negative delay problem in conventional delay definition at very slow slope and accurate delay handling becomes possible in logic simulation and logic synthesis

Keywords

CMOS digital integrated circuits; delays; integrated circuit design; integrated circuit modelling; large scale integration; logic design; timing; 0.5 micron; cell delay; cell-based LSI designs; dual threshold delay model; logic simulation; logic synthesis; low power design; nonlinear device characterization; sub-half micron CMOS devices; timing definition; wire delay; Capacitance; Circuit simulation; Delay effects; Inverters; Large scale integration; Region 2; Semiconductor device modeling; Threshold voltage; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518205

Filename

518205