A chip set architecture for programmable real-time MPEG2 video encoder

Author

Matsumura, Takeshi ; Segawa, H. ; Yamaoka, Hiroshi ; Nakagawa, Sachiko ; Ishihara, Koichi ; Kasezawa, T. ; Ajioka, Y. ; Maeda, Atsushi ; Yoshimoto, Masahiko

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo

fYear

1995

fDate

1-4 May 1995

Firstpage

393

Lastpage

396

Abstract

This paper describes a chip set architecture for a programmable video encoder based on the MPEG2 main profile at main level (MP@ML). The chip set consists of a Controller-LSI (C-LSI), a macroblock level Pixel Processor-LSI (P-LSI) and a Motion Estimation-LSI (ME-LSI). The chip set combined with synchronous DRAMs (SDRAM) supports the whole layer processing including rate-control and realizes the real-time encoding for ITU-R-601 resolution video (720×480 pixels at 30 frame/s) with glueless logic. The exhaustive motion estimation capability is scalable up to +-63.5/+-15.5 in the horizontal/vertical directions. This chip set solution can realize a low cost MPEG2 video encoder system with excellent video quality on a small PC card

Keywords

application specific integrated circuits; data compression; digital signal processing chips; large scale integration; motion estimation; real-time systems; video coding; video equipment; 345600 pixel; 480 pixel; 720 pixel; ITU-R-601 resolution video; MPEG2 video encoder; chip set architecture; controller LSI; exhaustive motion estimation capability; macroblock level pixel processor LSI; motion estimation LSI; programmable real-time encoder; synchronous DRAMs; Encoding; Hardware; Image reconstruction; Laboratories; Large scale integration; Motion control; Motion estimation; Pixel; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518210

Filename

518210