A variable round-robin arbiter for high speed buses and statistical multiplexers

The author presents the design of a high speed VLSI arbiter than is capable of performing round-robin scheduling for N requests with P possible priority levels. To improve the time and space complexities, the author proposes a centralized variable priority arbiter based on tree-structured cellular automata. Centralized implementation is permitted by the increasing wiring density on multiwire or printed circuit board technologies and the increasing number of I/O pins of VLSI technology. A sublinear arbitration speed is achieved by using a comparator tree and a token distribution mechanism for round-robin scheduling of N requests with P priority levels. The space complexity of the arbiter is O(N logP) and the time complexity of the arbiter is O(loglogP)logN. It is claimed that this is the first arbiter that can support variable priority arbitration with sublinear round-robin scheduling time complexity and linear space complexity. The behavior of the arbiter is evaluated and the possible enhancements to the arbiter are discussed