A low power 128×1-bit GaAs FIFO for ATM packet switcher

A low power 128×1-bit GaAs FIFO IC using two-phase dynamic FET logic (TDFL) has been successfully demonstrated. This FIFO was designed for use in an ATM switch application in order to reduce wiring complexity and to save power. Four CMOS FIFOs (66 MHz/4 W) can be replaced by one GaAs FIFO (500 mW) operating at 200 MHz, the speed targeted for this design. Higher speed operation was possible, but the 200 MHz operation allowed for the use of short, unterminated CMOS interconnections to avoid additional I/O power. The register array made use of the self-latching property, compact layout, and the low power dissipation of TDFL. The FIFO, which contains 270 TDFL gates and 1930 static gates, is shown to operate at 200 MHz with power dissipation of 100 mW. The measured maximum and minimum operating frequencies are 420 MHz and 100 MHz, respectively. The possibility of 10 times smaller power dissipation and a 4 times smaller system configuration of the ATM switcher using the GaAs FIFO compared with the CMOS case is shown