Title :
A 50,000 transistor packet-switching chip for the Starburst ATM switch
Author :
Chow, Peter ; Karchmer, David ; Chow, Peter ; White, Ron ; Ngai, Tony ; Hodgins, Paul ; Yeh, David ; Ranaweera, Jeewika ; Widjaja, Indra ; Leon-Garcia, Alberto
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
This paper describes the design and implementation of a 16×16 packet-switching chip that is used as the primary building block in a flexible, output-buffered, packet-switching architecture, called Starburst. This device contains 50,000 transistors implemented in a 1.2 μm CMOS process. Even with a very conservative two-phase clocking methodology and static logic, it can be clocked at 50 MHz. Sixteen chips have been used to construct a prototype 16×16 Starburst ATM switch with a maximum throughput of 2.5 Gbits/sec
Keywords :
CMOS logic circuits; VLSI; application specific integrated circuits; asynchronous transfer mode; clocks; integrated circuit design; packet switching; 1.2 micron; 2.5 Gbit/s; 50 MHz; CMOS process; Starburst ATM switch; maximum throughput; output-buffered architecture; packet-switching chip; primary building block; static logic; two-phase clocking methodology; Asynchronous transfer mode; CMOS logic circuits; CMOS process; Clocks; Computer architecture; Frequency; Packet switching; Prototypes; Switches; Throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518218
