The implementation of Viterbi decoder on TMS320C6201 DSP in W-CDMA system

This paper describes the design and implementation of a soft-decision Viterbi decoder on TMS320C6201 DSP developed by Texas Instruments (TI) in 1998. With an incomparable operating speed, which is 200 MHz (5 ns cycle time), the TMS320C6201 DSP can achieve the performance of up to 1600 million instructions per second (MIPS) and consequently has gained more and more popularity in many applications. In this paper, a soft-decision Viterbi decoder is implemented on the TMS320C6201 evaluation module (EVM) board with the code rate 1/3 and constraint length 9. Our original aim was to achieve a decoding rate of 32 kbits/s which is requested by the W-CDMA recommendation. To our delight, however, we have finally implemented a Viterbi decoder with the decoding rate of 88 kbits/s, which is quite comparable to what has been developed on FPGAs. We also mention some bottleneck problems of TMS320C6201 DSP and some applications of this kind of Viterbi decoder at the end of this paper