DocumentCode
2720545
Title
An 800 Mbps multi-channel CMOS serial link with 3× oversampling
Author
Kim, Sungjoon ; KyeongHo Lee ; Jeong, Deog-Kyoon ; Lee, Kyeongho ; Nowatzyk, Andreas G.
Author_Institution
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., South Korea
fYear
1995
fDate
1-4 May 1995
Firstpage
451
Lastpage
455
Abstract
A CMOS serial link is described that uses a digital PLL with 3× over-sampling to recover both clock and data. An implementation with 0.6 μm CMOS technology exhibits 800 Mbps operation with BER of less than 10E-12 for pseudo random number sequence. Chip area and power dissipation per channel at 800 Mbps are 2.1 mm×1.1 mm and 0.75 W, respectively
Keywords
CMOS digital integrated circuits; application specific integrated circuits; clocks; digital phase locked loops; 0.6 micron; 0.75 W; 800 Mbit/s; BER; chip area; clock recovery; data recovery; digital PLL; multi-channel CMOS serial link; oversampling; power dissipation; pseudo random number sequence; Bandwidth; CMOS technology; Charge pumps; Clocks; Frequency; Impedance matching; Integrated circuit technology; Phase locked loops; Sampling methods; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518222
Filename
518222
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