An area minimizing layout generator for random logic blocks

We present a new area minimizing layout generator and a new CMOS cell layout style with a regular and compact structure. The new structure, with power lines near the middle, uses less area for individual cells, makes intra- and inter-cell routing problems straightforward, allows easy embedding of feedthroughs in the cell, and enables output pins to occur at any grid location. Using an exact algorithm to generate static CMOS cells with a minimum number of diffusion breaks ensures that the width of the cells is minimized. An exhaustive search among the minimum width cells produces the minimum height cell. Interaction between the global router and the cell generator optimizes the locations of feedthroughs needed for the routing and the pin orderings for all cells. Detail routing merely requires a two or three layer channel router for over-the-cell routing. Our results show that circuits using the new cell layout style achieve significant area savings compared to the use of the existing MSU library and an industrial library of manually laid out compact cells