Logic block and routing considerations for a new SRAM-based FPGA architecture

Author

Tavana, Danesh ; Yee, Wilson ; Young, Steve ; Fawcett, Bradly

Author_Institution

Xilinx Inc., San Jose, CA, USA

fYear

1995

fDate

1-4 May 1995

Firstpage

511

Lastpage

514

Abstract

The XC5000 family of devices embodies the first Field Programmable Gate Array (FPGA) architecture optimized for sub-micron, three-layer-metal process technology. The architecture features a logic block structure with both coarse-grained and fine-grained elements and a rich hierarchy of routing resources. The I/O blocks are isolated from the core array to increase routability and facilitate process shrinks

Keywords

CMOS logic circuits; SRAM chips; field programmable gate arrays; integrated circuit layout; logic design; network routing; SRAM-based FPGA architecture; XC5000 family; coarse-grained elements; fine-grained elements; logic block structure; routing resources; submicron three-layer-metal process; Field programmable gate arrays; Logic arrays; Logic devices; Logic functions; Logic programming; Multiplexing; Programmable logic arrays; Registers; Routing; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-2584-2

Type

conf

DOI

10.1109/CICC.1995.518235

Filename

518235

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2720730