Title :
100 MHz, 0.55 mm2, 2 mW, 16-b stacked-CMOS multiplier-accumulator
Author :
Furuta, K. ; Ito, H. ; Wakabayashi, H. ; Nakajima, Kensuke ; Mogami, Tohru ; Horiuchi, T.K. ; Yamashina, M.
Abstract :
A 16-b multiplier-accumulator with stacked CMOS has been developed. It can be used for the digital signal processors which, as main parts of multimedia portable terminals, are required to have low power consumption and high processing speed. The stacked-CMOS logic circuit, which has high-speed and low-power characteristics, and optimization techniques are employed to attain a low power dissipation value of 2 mW at 100 MHz operation. Its area is 0.55 mm2, and the transistor density is two times that of conventional multiplier-accumulators. The fabrication technology is a 0.25-μm CMOS double layer Al process
Keywords :
CMOS logic circuits; circuit optimisation; digital signal processing chips; integrated circuit technology; multiplying circuits; 0.25 micron; 100 MHz; 16 bit; 2 mW; Al; CMOS double layer process; digital signal processors; fabrication technology; low-power characteristics; optimization techniques; power consumption; processing speed; stacked-CMOS multiplier-accumulator; transistor density; Adders; Circuit synthesis; Clocks; Delay; Digital signal processing; Energy consumption; MOSFETs; Pipeline processing; Power dissipation; Throughput;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518254
