DocumentCode
2721080
Title
An integrated data path synthesis algorithm based on network flow method
Author
Kim, Taewhan ; Liu, C.L.
Author_Institution
Lattice Semicond. Corp., Milpitas, CA, USA
fYear
1995
fDate
1-4 May 1995
Firstpage
615
Lastpage
618
Abstract
We present an integrated approach to the solution of the scheduling, allocation (register and interconnections), and binding problems in high-level synthesis. Our algorithm synthesizes a data path from an unscheduled-data flow graph with an objective of minimizing both the number of control steps and total design area. Unlike most of the prior approaches in which interconnections are determined only in the final step of the synthesis process in our approach, scheduling of operations binding of operations to functional units, and binding of variables to registers are performed simultaneously so that interconnections are determined optimally for each control step. The problem is formulated as a minimum cost maximum flow problem in a network which can be solved in polynomial time using the minimum cost augmentation method. Experimental results on a number of benchmark problems show that the approach is quite effective
Keywords
circuit layout CAD; data flow graphs; high level synthesis; integrated circuit interconnections; integrated circuit layout; scheduling; binding problem; high-level synthesis; integrated data path synthesis algorithm; interconnection allocation; minimum cost augmentation method; minimum cost maximum flow problem; network flow method; register allocation; scheduling; unscheduled-data flow graph; Algorithm design and analysis; Arithmetic; Computer science; Costs; Electric variables control; Hardware; Lattices; Network synthesis; Optimal control; Scheduling algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-2584-2
Type
conf
DOI
10.1109/CICC.1995.518258
Filename
518258
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