Title :
Technology decomposition for low-power synthesis
Author :
Panda, Rajendran ; Najm, Farid N.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
Technology decomposition and technology mapping are two potential stages for minimizing circuit power during logic synthesis. Since power in CMOS circuits is directly dependent on the extent of circuit switching activity, we present a novel procedure to construct a low-activity circuit structure in the technology decomposition stage. This would result in low-power circuits when mapped. The algorithm uses the transition density as a measure of switching activity and is applicable to both synchronous and asynchronous static circuits. Our results show power reductions of up to 48% (on average ≈10%), with little area or delay penalty
Keywords :
CMOS logic circuits; asynchronous circuits; integrated circuit design; logic CAD; sequential circuits; CMOS circuits; asynchronous static circuits; circuit switching activity; logic synthesis; low-activity circuit structure; low-power synthesis; synchronous static circuits; technology decomposition; transition density; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Delay; Logic circuits; Logic devices; Signal synthesis; Steady-state; Switching circuits;
Conference_Titel :
Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-2584-2
DOI :
10.1109/CICC.1995.518261
