Optimizing the timing center for high-speed parallel buses

As data rates continue to increase, the quality of the transmitted signal is not the only important factor in the design of modern high-speed I/O interfaces; accurate positioning of the receiver clock, in order to detect an incoming signal, is also critical. Modern high-speed I/O interfaces, including both parallel and memory buses (such as Elastic Interface, QuickPath Interconnect, HyperTransport, XDR DRAM, and GDDR5 DRAM buses), already include a data-training feature used to center the receiver clock. This paper describes the general principles used in various timing centering algorithms. Specifically, two different approaches, based on the worst-case eye opening and the median of eye fuzz, are compared. The timing center can drift significantly, due to temperature variation and low frequency supply voltage noise, and consequently requires periodic updates. This paper presents an efficient way to track this timing drift periodically. In mobile applications, some of the low-power modes of operations prohibit the use of the periodic timing calibration to minimize power consumption. A novel scheme to avoid this power consumption is also introduced.