Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer

Flexible design implementations are increasingly explored in digital communication applications to cope with diverse configurations imposed by the emerging communication standards. On the other hand, rapid hardware prototyping is a crucial requirement in system validation and performance evaluation under various use case scenarios. Adding flexibility, and hence increasing system complexity on one hand, and shrinking design time to meet with market pressure on the other hand, require a productive design approach ensuring final design quality. By eliminating the instruction set overhead, No- Instruction-Set-Computer (NISC) approach fulfills these design requirements offering static scheduling of datapath, automated RTL synthesis and allowing designer to have direct control of hardware resources. This paper presents a case study of an NISC-based implementation of a flexible low-complexity MIMO turboequalizer. The complete design and prototype flow, from architecture specification till FPGA implementation, is described in details. Using VC707 evaluation board integrating Xilinx Virtex-7 FPGA, the prototype of 2×2/4×4 spatially multiplexed MIMO system achieves a throughput of 115.8/62.4 Mega symbols per second at a clock cycle frequency of 202.67 MHz. Furthermore, the flexibility of the demonstrated prototype allows to support all communication modes defined in LTE, WiFi, WiMAX, and DVB-RCS wireless communication standards.