A High Speed Block Convolution Using Ancient Indian Vedic Mathematics

In digital signal processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, overlap-add method (OLA) and overlap-save method (OLS) can be considered. The OLA and OLS are well known efficient schemes for high-order filtering. The most commonly used implementation for digital filtering algorithms are digital signal processors, special purpose digital filtering chips and application specific integrated circuits (ASICs) for large volumes. In this paper, a high performance, high throughput and area efficient architecture for the field programmable gate array (FPGAs) implementation of block convolution process is proposed. The most significant aspect of the proposed method is the development of a multiplier architecture based on vertical and crosswise structure of ancient Indian Vedic mathematics and embedding it in OLA and OLS methods for improved efficiency. The coding is done in VHDL (very high speed integrated circuits hardware description language) and the FPGA synthesis is done using Xilinx Spartan library. The results shows that OLA and OLS method of block convolution implemented using Vedic multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplier architectures.