Abstract :
Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP (´above´ passivation), approach and a foundry level (´below´ passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail
Keywords :
integrated circuit interconnections; integrated circuit packaging; system-in-package; 3D SIC; 3D SIP; 3D WLP; 3D interconnection schemes; 3D system integration technologies; Si; electronic interconnection; electronic packaging; multilayer interconnect; vertical connections; wafer level packaging; CMOS technology; Electronics packaging; Integrated circuit interconnections; Nonhomogeneous media; Passivation; Semiconductor device packaging; Sensor arrays; Substrates; Tiles; Wiring;
Conference_Titel :
VLSI Technology, Systems, and Applications, 2006 International Symposium on
