DocumentCode :
2721994
Title :
Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology
Author :
Sakuma, Katsuyuki ; Smith, Kurt ; Tunga, Krishna ; Perfecto, Eric ; Wassick, Thomas ; Pompeo, Frank ; Nah, Jae-Woong
Author_Institution :
Microelectron. Div., IBM, Hopewell Junction, NY, USA
fYear :
2012
fDate :
May 29 2012-June 1 2012
Firstpage :
430
Lastpage :
435
Abstract :
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.
Keywords :
assembling; cooling; elemental semiconductors; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; scanning electron microscopy; silicon; C-SAM; C-mode scanning acoustic microscope; Pb-free flip chip packaging; Si; ULK layers; ULK stresses; ULK technology; assembled silicon chip; base plate; bonder head; bonding process; chip interconnects; chip package interaction issue; chip warpage; coefficient of thermal expansion mismatch; controlled collapse chip connection stresses/strains; conventional reflow process; die package; differential heating/cooling chip joining method; flip chip assembly; low-K dielectric constant device integration; noncontact white light reflectometry; nondestructive X-ray images; organic substrates; scanning electron microscope; substrate temperature; ultra low-k technology; warpage shape; Cooling; Heating; Laminates; Semiconductor device modeling; Silicon; Stress; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2012.6248866
Filename :
6248866
Link To Document :
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