Title :
Advanced flip-chip package solution for 28nm Si node and beyond
Author :
Liu, C.S. ; Chen, C.S. ; Lee, C.H. ; Tsai, H.Y. ; Pu, H.P. ; Cheng, M.D. ; Kuo, T.H. ; Chen, H.W. ; Wu, C.Y. ; Lii, M.J. ; Yu, Doug C H
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
fDate :
May 29 2012-June 1 2012
Abstract :
Next generation flip chip package with <;100um fine bump pitch is developed in a cost effective Bump-on-Trace (BOT) package structure for 28nm Si technology node. This is foreseen to be a mainstream for mobile applications in next generations. The key challenges of this new technology include warpage control of molded underfill (MUF) for <; 4 mils of thin die, packaging yield due to finer pitch of bumping/substrate design and thermal/mechanical effect on chip-package-interaction (CPI) [1-2]. CPI due to the use of fragile extreme low-k (ELK) dielectric material in the back-end-of-line (BEOL) layers has been fully characterized. The well-integrated Si/bump/package processes enable reliable CPI and assembly yield. An aggressive and reliable Si/bump/package design and CPI approaches are also discussed.
Keywords :
elemental semiconductors; flip-chip devices; low-k dielectric thin films; reliability; silicon; BEOL layers; BOT package structure; CPI reliability; MUF; Si; advanced flip-chip package solution; back-end-of-line layers; bump pitch; bump-on-trace package structure; bumping-substrate design; chip-package-interaction; fragile ELK dielectric material; fragile extreme low-k material; mobile applications; molded underfill; next generation flip chip package; size 28 nm; thermal-mechanical effect; warpage control; Assembly; Flip chip; Joints; Reliability; Silicon; Stress; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248867
