Digital clock frequency doubler

Author

Wadhwa, Sanjay K. ; Khan, Qadeer A. ; Misri, Kulbhushan ; Muhury, Deeya

Author_Institution

Freescale Semicond. India Pvt. Ltd., Bangalore

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

15

Lastpage

18

Abstract

A digital clock frequency doubler capable of handling large variation in input duty cycle and PVT (process, voltage and temperature) is presented. Unlike the conventional clock frequency doublers, the proposed circuit doesn´t require 50% duty cycle for doubling the input clock frequency and consumes lower silicon area. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in PVT. The circuit has been designed in 90nm CMOS process with input frequency range of 10MHz to 30MHz and silicon results show less than 0.2% of average frequency error

Keywords

CMOS integrated circuits; clocks; frequency multipliers; timing circuits; 10 to 30 MHz; 90 nm; CMOS process; digital algorithm; digital clock frequency doubler; duty cycle; frequency stability; inbuilt PVT compensation mechanism; CMOS process; Circuit stability; Clocks; Costs; Frequency; Jitter; Phase locked loops; Silicon; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554445

Filename

1554445