Test Case Generation from UML State Machine Diagram: A Survey

Author

Aggarwal, M. ; Sabharwal, Sangeeta

Author_Institution

Dept. of Comput. Sci. & IT, Netaji Subhas Inst. of Technol., Delhi, India

fYear

2012

fDate

23-25 Nov. 2012

Firstpage

133

Lastpage

140

Abstract

UML is widely accepted and practiced in industries for modeling and design of software systems. Software requirements and design are very important parts of software development, which must be validated and verified before implementation. UML State Machine diagram is an important formalism to model the dynamics of the system. In this paper, a comparative study of the test case generation techniques from UML State Machine diagram has been done. This study is an attempt to find out the work that has already been done in this field and various aspects of UML state machines that have been considered for generating test cases. Finally, this paper presents a scope to generate test data for complex state machine involving concurrent states and events.

Keywords

Unified Modeling Language; finite state machines; formal specification; program testing; UML state machine diagram; concurrent events; concurrent states; software design; software requirements; software systems; test case generation techniques; Computational modeling; Databases; Genetic algorithms; Object oriented modeling; Software; Testing; Unified modeling language; Test Cases; Test Data; Testing; UML state chart diagram; UML state machine;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Technology (ICCCT), 2012 Third International Conference on

Conference_Location

Allahabad

Print_ISBN

978-1-4673-3149-4

Type

conf

DOI

10.1109/ICCCT.2012.34

Filename

6394682