65nm SOI CMOS Technology for High Performance Microprocessor Application

Author

Fung, Samuel K H ; Grudowski, P.A. ; Wu, C.H. ; Kolagunta, V. ; Cave, N. ; Yang, C.T. ; Lian, S.J. ; Adams, V. ; Zia, O. ; Min, B. ; Grove, N. ; Chen, K.H. ; Liang, W.J. ; Lee, D.H. ; Huang, H.T. ; Cheek, J. ; Tuan, H.C.

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Hsinchu

fYear

2006

fDate

24-26 April 2006

Firstpage

1

Lastpage

2

Abstract

This paper presents a state-of-the-art 65nm SOI CMOS transistor technology target for high performance microprocessor application. N/PFET shows short channel control meeting manufacturing margin at 32/35nm respectively. By using dual contact etch stop layer (CESL) process, PFET ion is 875muA/mum at I_off=100nA/mum (V _DD=1.2V), which is 65% increase over 90nm node. The 65nm technology also offers SRAM cell sizes ranging from 0.499mum² to 0.64mum² for various speed and density requirement

Keywords

MOSFET; SRAM chips; microprocessor chips; nanotechnology; silicon-on-insulator; 1.2 V; 65 nm; CESL process; N-PFET device; PFET ion; SOI CMOS technology; SOI CMOS transistor technology; SRAM cell; contact etch stop layer process; high performance microprocessor; CMOS technology; Compressive stress; Germanium silicon alloys; Microprocessors; Random access memory; Silicon compounds; Silicon germanium; Thermal degradation; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2006 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0181-4

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2006.251065

Filename

4016601