DocumentCode
2722277
Title
High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires
Author
Fischer, A.C. ; Bleiker, S.J. ; Somjit, N. ; Roxhed, N. ; Haraldsson, T. ; Stemme, G. ; Niklaus, F.
Author_Institution
KTH R. Inst. of Technol., Stockholm, Sweden
fYear
2012
fDate
May 29 2012-June 1 2012
Firstpage
541
Lastpage
547
Abstract
Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (>;8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched through-silicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio state-of-the-art TSVs for e.g. interposer, MEMS and RF applications.
Keywords
coatings; elemental semiconductors; etching; insulation; integrated circuit manufacture; magnetic devices; self-assembly; silicon; three-dimensional integrated circuits; wires (electric); 3D integration; Au-Ni; MEMS application; MEMS-based transducer; RF application; Si; electrical characteristic; gold-coated nickel rod; gold-coated nickel wire; high aspect ratio TSV fabrication technique; high-aspect ratio through silicon metal; insulation; interposer application; magnetic self-assembly; manufacturing technology; metal deposition; parasitic capacitance; shorter signal length; three-dimensional integration; through silicon vias; through-silicon-via hole etching; vertically stacked die interconnection; Assembly; Fabrication; Gold; Nickel; Silicon; Through-silicon vias; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4673-1966-9
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2012.6248882
Filename
6248882
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