A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy Technology (GORES MOSFET) for 32nm node and beyond

Author

Kikuchi, Y. ; Tateshita, Y. ; Kataoka, T. ; Wang, J. ; Miyanami, Y. ; Yamagishi, N. ; Ikuta, T. ; Yamamoto, Y. ; Hiyama, S. ; Ugajin, H. ; Ikeda, H. ; Fujita, S. ; Yamamoto, R. ; Kanda, S. ; Imoto, T. ; Kashiwadate, S. ; Tagawa, Y. ; Iwamoto, H. ; Ohno, T

Author_Institution

Semicond. Solutions Network Co., Sony Corp., Kanagawa

fYear

2006

fDate

24-26 April 2006

Firstpage

1

Lastpage

2

Abstract

We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing parasitic resistance and suppression of the short channel effect (SCE) (Tateshita, 2005). As a matter of course, it has the USJ and the low parasitic resistance (LPR) for 32nm node with in-situ doped selective Si epitaxy (ISDSE)

Keywords

MOSFET; elemental semiconductors; epitaxial growth; nanotechnology; semiconductor doping; semiconductor growth; silicon; 32 nm; GORES MOSFET; ISDSE; SCE; Si; USJ; gate overlapped raised extension structure; in-situ doped selective Si epitaxy technology; parasitic resistance; planar transistor; short channel effect; ultra shallow junction; Annealing; Dielectrics; Electrodes; Electronic mail; Epitaxial growth; Impurities; MOSFET circuits; Shape measurement; Solid lasers; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2006 International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0181-4

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2006.251066

Filename

4016602