Title :
Mechanically compliant lead-free solder metallurgy: The key element in enabling extreme low-k large-die flip chip devices
Author :
Pang, Mengzhi ; Kaufmann, Matt ; Sze, Henry ; Sharifi, Reza ; Tan, Keith ; Neo, Chong Wei ; Ramakrishna, Ram ; Karikalan, Sam ; Khan, Reza
Author_Institution :
Broadcom Corp., San Jose, CA, USA
fDate :
May 29 2012-June 1 2012
Abstract :
Significant challenges are encountered to enable large-die fine-pitch lead-free-bump flip chip devices, especially with extreme low-k (ELK) silicon technology for 40 nm and beyond. Such failures are often observed as die ELK stack-up fractures, lead-free bump cracking, underfill delamination, high warpage-induced BGA reliability issues, etc. The underlying root cause can be attributed to elevated thermo-mechanical stress within the packaging when lead-free bump material is used for the die-to-packaging interconnect. This paper presents an innovative approach to addressing these technical problems by applying mechanically compliant lead-free bump metallurgy. In conjunction with several other aspects of assembly and packaging material optimization, this solution is capable of delivering 100% lead-free flipchip packaging with a die size of up to 20×20 mm and a package size of up to 52.5×52.5 mm per side.
Keywords :
assembling; ball grid arrays; delamination; elemental semiconductors; failure analysis; fine-pitch technology; flip-chip devices; fracture; interconnections; low-k dielectric thin films; metallurgy; reliability; silicon; solders; ELK silicon technology; die ELK stack-up fractures; die-to-packaging interconnect; extreme low-k large-die flip chip devices; extreme low-k silicon technology; high warpage-induced BGA reliability; large-die fine-pitch lead-free-bump flip chip devices; lead-free bump cracking; lead-free bump material packaging; lead-free flip chip packaging; material optimization assembly; material optimization packaging; mechanically compliant lead-free solder bump metallurgy; size 40 nm; thermo-mechanical stress; underfill delamination; Lead; Packaging; Soldering; Stress; Substrates; Tin;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248891