DocumentCode
2722429
Title
Precharged SRAM cell for ultra low-power on-chip cache
Author
Aly, Ramy E. ; Bayoumi, Magdy A.
Author_Institution
Adv. Comput. Studies Center, Louisiana Univ., Lafayette, LA, USA
fYear
2005
fDate
25-28 Sept. 2005
Firstpage
95
Lastpage
98
Abstract
This paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0.18nm technology. On the sleep mode, the proposed cell reduces the leakage current by 60% for 70nm technology.
Keywords
SRAM chips; cache storage; leakage currents; low-power electronics; nanotechnology; 0.18 nm; 70 nm; HSPICE simulation; dynamic power; leakage current; leakage power; on-chip cache; precharged SRAM cell; ultra low power technique; voltage swing; CMOS technology; Capacitance; Degradation; Delay; Energy consumption; Leakage current; Random access memory; Temperature; Transistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2005. Proceedings. IEEE International
Print_ISBN
0-7803-9264-7
Type
conf
DOI
10.1109/SOCC.2005.1554467
Filename
1554467
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