Ultra-Thin SOI CMOS Using Laser Spike Anneal

We have investigated the impact of laser spike anneal (LSA) on the performance of ultra-thin SOI MOSFETs. LSA was found to significantly reduce the parasitic external resistance in UTSOI devices. Reduced external resistance in conjunction with improved gate activation resulted in a substantial improvement in nFET performance. A conventional spike RTA followed by LSA at 1300C enhances nFET drive current, I_ON, by 20% and the effective drive current, I_OFF, by 30% (at I_OFF equiv 1 muA/mum). The RTA+LSA approach was found to have a smaller impact on pFET performance. This is attributed to boron loss due to segregation into the buried oxide (BOX) during the RTA. The RTA+LSA process also resulted in improved AC performance (~ 10% improvement in ring oscillator stage delay at fixed leakage current) compared to an RTA-only process. We have found that an LSA-only process significantly suppresses boron segregation and increases dopant activation, resulting in a 50% reduction in the p-type sheet resistance when compared to a conventional high temperature RTA-only process. The introduction of LSA provides a path for high performance UTSOI CMOS