Mapping of partial reconfigurable data flows to Xilinx FPGAs

Recently, commercially available Xilinx FPGAs have started to support partial run time reconfiguration (RTR) wherein part of the FPGA can be reconfigured while the rest of the FPGA logic is functioning. However, access to the FPGA for RTR is not completely flexible and needs a systematic partitioning of the FPGA fabric into static and reconfigurable partitions within certain pretty tight constraints. Modules mapped to different partitions need to communicate using specialized macros. In this paper, we present a method for mapping a data flow requiring partial RTR to the Xilinx FPGAs. We develop a cost function that guides the mapping of nodes to these partitions by attempting to minimize the communication cost while ensuring that the required RTR is completed within certain time constraints