DocumentCode
2722771
Title
Novel 7T sram cell for low power cache design
Author
Aly, Ramy E. ; Faisal, Md I. ; Bayoumi, Magdy A.
Author_Institution
Center of Adv. Comput. Studies, Univ. of Louisiana at Lafayette, LA
fYear
2005
fDate
19-23 Sept. 2005
Firstpage
171
Lastpage
174
Abstract
Low-power on-chip cache is a crucial part in many applications. Conventional write operation depends on discharging/charging large bit lines capacitance which causes high power consumption. We propose a 7T SRAM cell that only depends on one of the bit lines during a write operation and reduce the write power consumption. HSPICE simulation shows that at least 49% write power saving, higher stability, and no performance degradation with additional 12.25% silicon area
Keywords
SRAM chips; cache storage; integrated circuit design; low-power electronics; 7T SRAM cell; HSPICE simulation; low power cache design; on-chip cache; write operation; CMOS technology; Capacitance; Degradation; Delay; Energy consumption; Feedback; MOSFETs; Random access memory; Stability; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2005. Proceedings. IEEE International
Conference_Location
Herndon, VA
Print_ISBN
0-7803-9264-7
Type
conf
DOI
10.1109/SOCC.2005.1554488
Filename
1554488
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