Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration

Tradeoffs associated with the use of the IEEE 1149.1 serial test interface for wafer-scale-integrated designs are identified. Test circuitry area overhead and yield loss are weighed against the benefits of reduced I/O (input/output) area and improved wafer testability. Where the area overhead of a complete 1149.1 interface is not justifiable for small cells, a simple scan interface which still allows for compliance with the 1149.1 standard at the full wafer system level is proposed. It is shown that the additional test area required may be more than compensated for by the savings in I/O probe pad area. Through a yield analysis driven by the relative areas of the constituent cells, the authors provide a systematic framework for the process of placing 1149.1 test capabilities within a monolithic wafer-scale-system design