On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression

One must be very careful in utilizing the available on-chip memory space in embedded MpSoC architectures, which may be very challenging due to data sharing among processors. This paper proposes and evaluates an on-chip memory space management strategy based on data compression. The proposed strategy first uses a compiler analysis that reveals the order in which different data blocks are required by the application. After that, it builds an integer linear programming based representation of the on-chip memory space management problem, and solves it using a publicly-available integer linear programming tool. The solution gives the optimum order in which data blocks should be compressed and decompressed to minimize execution cycles or energy consumption under an on-chip memory capacity limit