DocumentCode
2722807
Title
Mixed-mode ATPG under input constraints
Author
Glover, C. Thomas
Author_Institution
Motorola Inc., Austin, TX, USA
fYear
1990
fDate
10-14 Sep 1990
Firstpage
142
Lastpage
151
Abstract
A pragmatic method of mixed-mode automatic test pattern generation (ATPG) which can operate under constrained inputs is presented. The author discusses fundamental modifications to traditional ATPG which allow tests to be generated for nontrivial circuits containing switch-level primitives. The program used, SPHINX, achieves reasonable fault coverages for mixed-mode circuits larger than those previously reported
Keywords
application specific integrated circuits; automatic testing; fault location; integrated circuit testing; logic testing; ASIC; IC testing; SPHINX; constrained inputs; fault coverages; input constraints; logic testing; mixed-mode automatic test pattern generation; switch-level primitives; Algebra; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Feeds; Logic testing; Switches; Switching circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1990. Proceedings., International
Conference_Location
Washington, DC
Print_ISBN
0-8186-9064-X
Type
conf
DOI
10.1109/TEST.1990.114012
Filename
114012
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