Strained-SOI Technology for High-Speed CMOS Operation

The strained-Si technology, including biaxial/uniaxial strain and local stress techniques, has been widely studied for the carrier mobility enhancement using strained-Si channel layers. In order to realize high-speed CMOS operation, the SOI technology as well as the strained-Si is the key issue, because of the suppressed Coulomb scattering and the lower drain junction capacitance [Mizuno et al., 2000]. Using the strained-Si on (100)-surface SGOI substrate (strained-SOI) technology, we have experimentally demonstrated high performance CMOS devices [Mizuno et al., 2003]. However, the hole mobility of (100)-surface strained-SOI is still lower than the electron one. In this paper, we have discussed strained-SOI technology for further improvement of CMOS operation speed. Firstly, we have developed (110)-surface strained-SOI MOSFETs to realize much higher hole mobility [Mizuno et al., 2005]. We have achieved that the (110)-surface hole mobility is much higher than that of the (100)-surface strained-SOIs. Secondly, we have proposed the source-heterojunction-MOS-transistor (SHOT) for future ballistic transport transistors, using the strained-SOI substrates [Mizuno et al., 2005]. We have demonstrated that the transconductance of SHOTs is enhanced because of the high velocity electron injection from the source into the channel, using the excess kinetic energy due to the source heterojunction band offset