Designing for signal integrity in wave-pipelined SOC global interconnects

This paper discusses the importance of wave-pipelining to enhance throughput performance and maintain good signal integrity on global interconnects in a system-on-chip (SOC). It is shown that wave-pipelining results in 50% reduction in the active line overshoot voltage and 75% reduction in the quiet line crosstalk voltage as compared to a single driver interconnect in the presence of severe inductive coupling. A clock-skew-insensitive receiver circuit to synchronize the communication on wave-pipelined interconnects between different clock domains in SOC is also proposed and validated with HSPICE