• DocumentCode
    2723017
  • Title

    Zero defects or zero stuck-at faults-CMOS IC process improvement with IDDQ

  • Author

    Soden, Jerry M. ; Fritzemeier, Ronald R. ; Hawkins, Charles F.

  • Author_Institution
    Sandia Nat. Lab., Albuquerque, NM, USA
  • fYear
    1990
  • fDate
    10-14 Sep 1990
  • Firstpage
    255
  • Lastpage
    256
  • Abstract
    The authors suggest that continuous quality improvement with the goal of zero defects requires a physical defect metric which goes beyond 100% SAF (stuck-at-fault) coverage. It is further suggested that I DDQ testing is a highly efficient technique for detecting most dominant types of CMOS IC defects and therefore should be considered for the manufacture of high-quality, high reliability CMOS ICs
  • Keywords
    CMOS integrated circuits; electric current measurement; fault location; integrated circuit testing; production testing; quality control; CMOS IC defects; IC testing; QC; zero defects; zero stuck-at faults; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Delay; Integrated circuit interconnections; Integrated circuit testing; Logic testing; Semiconductor device modeling; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1990. Proceedings., International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-8186-9064-X
  • Type

    conf

  • DOI
    10.1109/TEST.1990.114026
  • Filename
    114026
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2723017