GTL high speed I/O in 3D ICs for TSV and interconnect signal integrity characterization

This paper focuses on TSV and interconnect signal integrity characterization of 3D IC embedded test structures that measure GTL high speed I/O performance. The three Tiers of a CMOS 3D IC were fabricated by MIT Lincoln Laboratory in a 150nm SOI process bonded together and the test structures were ball-bonded on to a custom FR-4 board designed for matched 50Ω microwave and high speed transient measurements. The comparison between on-chip and FR-4 board measurement results for TSV and interconnect signal integrity characterization will be shown and analyzed using equivalent electrical models. In addition, the paper reports extensive additional on-board measurements including, 1) 3D IC GTL I/O response to varying data patterns, 2) Edge timing comparing GTL signals launched from several 3D IC Tiers simultaneously to the same I/O output, and 3) GTL I/O performance under degraded environmental conditions in the 3D IC such as reduced bias.