A Clock Isolation Method For Complex SoC Designs

This paper describes a novel clock isolation method that resolves issues in logical and physical synthesis caused by using clock as data to qualify signals or switch data flows in complex SoC designs. The principles of the method and implementation guidelines are described in detail. The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow. The clock isolation method has been successfully implemented and verified in a complex SoC design