Title :
Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration
Author :
Sheu, S.S. ; Lin, Z.H. ; Lin, C.S. ; Lau, J.H. ; Lee, S.H. ; Su, K.L. ; Ku, T.K. ; Wu, S.H. ; Hung, J.F. ; Chen, P.S. ; Lai, S.J. ; Lo, W.C. ; Kao, M.J.
fDate :
May 29 2012-June 1 2012
Abstract :
In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC´s 0.18μm process (FEOL) and ITRI´s BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.
Keywords :
driver circuits; integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D IC integration; ITRI BEOL process; TSMC FEOL process; TSV; TSV transmission performance analysis; chip bus TEG; chip stack; data transmission performance; electrical characterization; on-chip bus driver; receiver; size 0.18 mum; size 100 mum; size 30 mum; test element group; through silicon vias; transceiver; voltage 1.8 V; Data communication; Power demand; Semiconductor device measurement; Strontium; Through-silicon vias; Vehicles;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4673-1966-9
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2012.6248933
