Co-design and optimization of a 256-GB/s 3D IC package with a controller and stacked DRAM

This paper presents a double-sided flip-chip package. The package consists of a memory controller on one side of an organic substrate, and 3D-stacked, disaggregated memory chips, integrated with TSVs, on the opposite side. Thermal isolation is one of the key motivations for this configuration. Co-design of all physical layers is required to optimize the integrated 3D package within electrical and manufacturing constraints. Double-sided flip-chip packaging also presents unique challenges in the design of the power delivery network (PDN). A pre-layout design strategy is described, which optimizes the PDN design across 11 power domains to meet stringent impedance targets.