FPGA implementation of the "pyramids" block cipher

The "PYRAMIDS" block cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in C++ code. In this paper, a hardware implementation of the algorithm, using field programmable gate arrays (FPGA), is presented. In this work, the authors discussed the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, a detailed comparison with other implemented standard algorithms was presented. In addition, the floor plan as well as the circuit diagrams of the various micro-architecture modules was presented