Design and implementation of phase correlation based motion estimator

Author

Molino, Andrea ; Vacca, Fabrizio ; Masera, Guido

Author_Institution

Dipt. di Elettronica, Politecnico di Torino

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

291

Lastpage

294

Abstract

This paper describes an architecture for the efficient computation of motion estimation based on phase correlation (PC). The entire block has been implemented on a Virtex2 FPGA, and particular care has been posed on the throughput requirements in a video coding framework. These tight requirements lead to the need for high performance solutions for both the discrete Fourier transform (DFT) block and the vector normalization engine. The DFT stage has been implemented with a pipelined decimation in time (DIT) flow, while a multiplierless CORDIC-based structure is used for the vector normalization

Keywords

discrete Fourier transforms; field programmable gate arrays; logic design; motion estimation; video coding; Virtex2 FPGA; discrete Fourier transform; motion estimator; multiplierless CORDIC-based structure; phase correlation; pipelined decimation; vector normalization engine; video coding framework; Computer architecture; Discrete Fourier transforms; Engines; Field programmable gate arrays; Fourier transforms; Motion estimation; Phase estimation; Throughput; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554513

Filename

1554513