Sequencer Per Pin test system architecture

A novel digital functional test system architecture, called Sequencer Per Pin in which the timing and waveform generation hardware work with a sequence of events in the same manner as an IC timing/logic simulator, is presented. This architecture implements tests as sequences of events for each pin, synchronized by global period markers. This makes it possible to perform complex tests on VLSI integrated circuits without requiring extensive program development and debugging efforts. The architecture is more flexible than previous designs, permitting more precise implementation of simulation data with fewer restrictions. The event sequence concept allows significant reduction in test pattern storage requirements and optimizes this feature even further by permitting run-time assignment of pin data, avoiding duplications of test patterns and test programs for different package configurations