A scalable VLSI architecture for binary prefix sums

The task of computing binary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. The paper describes a scalable VLSI architecture for the BPS problem. The authors adopt as the central theme of this effort, the recognition of the fact that the broadcast delay incurred by a signal propagating along a bus is, at best, linear in the distance traversed. Thus, one of the design criteria is to keep buses as short as possible. In this context, the main contribution is to show that one can use short buses in conjunction with shift switching to obtain a scalable VLSI architecture for the BPS problem